1. Field of the Invention
The present invention is generally related to the manufacture of semiconductor devices and, more particularly, to a process of making tungsten contact studs without etching oxide or oxide-etch stop and forming tungsten liners for interconnection metallurgy. The invention also relates to providing an improved single metallurgical system for forming both ohmic as well as high- and low-barrier Schottky contacts and an integral metallurgical structure comprised of interconnection lines and contact or interlevel via studs.
2. Description of the Prior Art
An integrated circuit (IC) generally includes a semiconductor substrate in which a number of device regions are formed by diffusion or ion implantation of suitable dopants. This substrate usually involves a passivating and an insulating layer required to form different device regions. The total thickness of these layers is usually less than one micron. Openings through these layers (called contact holes) allow electrical contact to be made selectively to the underlying device regions. A conducting material is used to fill these holes, called via studs, which then make contact to semiconductor devices.
One of the techniques for making via studs employs a selective tungsten process. In this method, tungsten plugs are made by selective deposition in the contact holes. However, the deposition is through nucleation phenomenon which is difficult to control, resulting for example in missing studs or tungsten being deposited at unwanted sites. Additionally, during processing fluorine entrapment and silicon encroachment may take place resulting in poor circuit yield and low reliability.
Another process for making plugs is the Damascene method. In this method a layer of alumina and a layer of an oxide insulator is deposited, contact holes aligned to the semiconductor devices are etched, a blanket layer of aluminum metallurgy or tungsten is deposited, and then the excess metal is removed by etching or by chemical-mechanical polishing. The layer of alumina acts as an etch barrier while oxide insulator is being etched. The alumina layer is subsequently removed by a suitable etchant. However, a problem with this method is the undercut of alumina where tungsten is deposited by chemical vapor deposition (CVD), reducing the separation between the adjacent studs, thereby causing leakage or shorts.
Various aspects of via stud metallurgy are described in U.S. Pat. Nos. 4,933,303 to Mo, 4,855,252 to Peterman et al., 4,879,257 to Patrick, and 4,721,689 to Chaloux et al. Mo discloses a process in which metal lines and studs are processed in two different steps. In the Mo process, metal planarization is through selective tungsten deposition which is known to suffer from repeatability. Peterman et al. disclose a process in which metal is deposited by plain evaporation or sputtering into a deep cavity. This approach causes seams in the metal, and blanket Reactive Ion Etch (RIE) for planarization will preferentially attack along these seams, most probably chewing out the metal from the stud area. Patrick discloses a process of making studs only. Chaloux et al. discloses a process wherein the stud is defined by Damascene process and the metal line pattern is defined in separate process steps by ion etching. The Chaloux et al. process, like that of Mo, involves oxide deposition after the metal lines are defined. This method is known to suffer from voids in the oxide between the closely spaced metal lines. Thus, despite repeated efforts in the prior art, problems of leakage, short circuits, etc., remain and better methods for making contact studs need to be developed.